The energy efficiency of computation has seen a remarkable trend of exponential improvement over the past 70 years.1
Since the 1960s, this advancement was largely driven by the miniaturization of metal–oxide–semiconductor field-effect transistors (MOSFETs) whose lateral dimensions have reached below 100 nm in the year 2003, marking the beginning of the nanoelectronics era. Since then, further improvements have been enabled by materials innovations (e.g., strain engineering and gate oxides with high relative permittivity εr) and the adoption of new device concepts (FinFET and fully depleted silicon on insulator technology). However, in recent years, the energy efficiency improvements in nanoelectronics have begun to slow down as we are approaching practical as well as fundamental physical limits…
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This article is excerpted from “Progress and future prospects of negative capacitance electronics: A materials perspective,” APL Mater. 9, 020902 (2021), https://doi.org/10.1063/5.0032954 (CC BY 4.0)
Cite this article
M. Hoffmann, S. Slesazeck, and T. Mikolajick, “Progress and future prospects of negative capacitance electronics: A materials perspective,” Am. Ceram. Soc. Bull. 2022, 101(3): 24–29.
About the Author(s)
Stefan Slesazeck is a researcher in NaMLab gGmbH at the Dresden University of Technology (TU Dresden). Thomas Mikolajick is a researcher in the Institute of Semiconductors and Microsystems at TU Dresden. Michael Hoffmann was a researcher in NaMLab gGmbH at TU Dresden and is now a postdoctoral scholar at the University of California, Berkeley. Contact Hoffmann at michael.hoffmann190@gmail.com.
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