The world’s digital data volume is expanding rapidly, driven by the adoption of big data and artificial intelligence-based systems.
With this expansion, the energy required to operate data centers is also increasing. As a result, scientists and engineers must develop new computer components and paradigms that can enable both high processing speeds and low power consumption.
In October 2024, Semiconductor Energy Laboratory Chairman and CEO Shunpei Yamazaki delivered the Rustum Roy Lecture at ACerS Annual Meeting on the development of indium oxide-based semiconductors to replace silicon electronics. In July 2025, he and his colleagues published an open-access paper—excerpted below—that elaborates on this development.
Oxide ceramic large-scale integration device for putting the brakes on global boiling accelerated by artificial intelligence age computers
From S. Yamazaki et al., IJCES 2025, 7(4): e70011. Read the full article here.
Climate change caused by global boiling, which is a factor in natural disasters, is a serious social problem.
One of the factors that could be considered a cause of global boiling is the rapid progress and widespread use of artificial intelligence (AI). Thus, hardware in the era of AI, such as servers, requires both high processing speed and low power consumption as a measure against global boiling.
One oxide semiconductor material, indium gallium zinc oxide (IGZO), was first synthesized in the world by N. Kimizuka in 1985, and its use as a semiconductor device was reported in 1987.1 Furthermore, in 1991, research results relating to the phase diagram for the In2O3–Ga2ZnO4–ZnO system were published.2 Subsequently, in 2004, field-effect transistor (FET) characteristics using amorphous IGZO were reported.3 We discovered c-axis aligned crystalline IGZO (CAAC-IGZO) in 2009.4,5
Research on oxide semiconductor materials continued even after the discovery of IGZO. In particular, crystal indium oxide with higher mobility than IGZO has attracted attention in recent years. We first proposed single crystal indium oxide and its application in large-scale integration in 2011 and have since continued to investigate its uses.
As reported at the 70th Annual IEEE International Electron Devices Meeting,6 we developed a 3-Mbit dynamic random-access memory (DRAM) device that includes crystal indium oxide. This DRAM is monolithically stacked over a silicon complementary metal oxide semiconductor and includes vertical capacitors and vertical channel FETs (channel hole diameter: 60 nm) over the vertical capacitors. According to high-speed verification, the DRAM operated normally even with a read time of 5 nanoseconds (2.0 V) and a write time of 5.5 nanoseconds (1.9 V).
In comparison with conventional vertical channel FETs that contain IGZO as a channel material, the vertical channel FETs that contain crystal indium oxide exhibited an on-state current that was higher by 8.3-fold. Furthermore, an 81% reduction in read time and an 89% reduction in write time were estimated when the gate electrode line was pulled up to be away from the source electrode to reduce the parasitic capacitance; that is, the read/write time was shortened due to the optimization of the vertical channel FET structure by including crystal indium oxide as a channel material in place of IGZO.
According to the retention measurement results, a pass ratio of 99% was maintained at 125°C even after a retention time of 100 seconds, which is 1,563 times longer than the general DRAM refresh time of 64 milliseconds. Thus, reductions in the refresh frequency and standby power are expected. This DRAM structure has potential for application into high-bandwidth memory that is die-stacked DRAM, the demand of which is increasing for AI.
Another application example is our analog AI system, in which oxide semiconductor FETs are monolithically stacked over silicon FETs.7 This analog AI system utilizes the subthreshold region of the silicon FETs for multiply–accumulate operations in the current mode.
Because a slight fluctuation in voltage in the subthreshold region causes a crucial fluctuation in the output current, the analog memory requires extremely high retention characteristics. Considering this context, an oxide semiconductor FET that enables a 1017 on/off ratio is regarded as a suitable device for analog AI systems. Our fabricated chip retains higher than 90% classification accuracy even after five hours have passed, which means that this chip achieves better data retention characteristics.
General analog AI systems consume a large amount of power in digital-to-analog (DA) and analog-to-digital (AD) conversion. In contrast, our fabricated system adopts a setup of executing analog computing in multilayer networks without AD conversion to reduce the number of times of DA/AD conversions and the number of data path circuits, resulting in reducing the power consumed by DA/AD conversion. Owing to this configuration, this system succeeded in executing the MNIST handwritten digit classification task with a low energy of 1.1 nJ/classification and an accuracy of 91.6% without a weight refresh for as long as five hours. This analog AI system has potential comparable to a human brain in the ultimate form of a low-energy device.
As a display with oxide semiconductor FETs, we fabricated a high-resolution, high-luminance (3,207 ppi and 15,000 cd/m2) augmented/virtual reality display system with 1.50 inches diagonally.8 This display system has a stacked-layer structure that includes a silicon circuit as the bottom layer, an oxide semiconductor pixel circuit layer over the silicon circuit, and an organic electroluminescence layer as the uppermost layer.9
Powerchip Semiconductor Manufacturing Corporation (PSMC), a Taiwanese company, successfully fabricated a 12-inch (300-mm) wafer based on our technology for application in augmented/virtual reality. PSMC is now addressing the commercialization of augmented/virtual reality systems by adopting our technology for the first time in the world.
In conclusion, our oxide semiconductor device technology can help reduce the power consumed by AI, which could be a key to solving global boiling.
Cite this article
L. McDonald, “Indium oxide semiconductors for low-power AI systems,” Am. Ceram. Soc. Bull. 2026, 105(1): 42–43.
About the Author(s)
Lisa McDonald is editor and science writer at The American Ceramic Society (Westerville, Ohio). Contact McDonald at lmcdonald@ceramics.org.
Issue
Category
- Electronics
- Energy materials and systems
- Manufacturing
Article References
1N. Kimizuka and T. Mohri, “Compound having a hexagonal layer structure represented by InGaZn2O5 and its manufacturing method,” Japanese Patent JPS63239117A. Granted 5 Oct. 1988. https://patents.google.com/patent/JPS63239117A
2M. Nakamura, N. Kimizuka, and T. Mohri, “The phase relations in the In2O3–Ga2ZnO4–ZnO system at 1350°C,” Journal of Solid State Chemistry 1991, 93(2): 298–315.
3K. Nomura et al., “Room-temperature fabrication of transparent flexible thin-film transistors using amorphous oxide semiconductors,” Nature 2004, 432: 488–492.
4S. Yamazaki et al., “Semiconductor device,” Japanese Patent JP5172918B2. Granted 27 March 2013. https://patents.google.com/patent/JP5172918B2
5S. Yamazaki et al, “Transistor and display device comprising oxide semiconductor layer,” United States Patent US9935202. Granted 3 April 2018. https://patents.google.com/patent/US9935202B2
6S. Miyata et al., “Vertical-channel crystalline In2O3 FET with a pulled-up gate, monolithically stacked on Si CMOS, achieving 112.2 µA/µm on-state current,” 70th IEEE Int Electron Devices Meeting 2024.
7K. Tsuda et al., “A 1.1-nJ/classification true analog current computing on multilayer neural network with crystalline-IGZO/Si-CMOS monolithic stack technology,” IEEE Journal of the Electron Devices Society 2024, 12: 594–604.
8S. Fukuzaki et al., “High-luminance and highly reliable tandem OLED display including new intermediate connector designed for photolithography applications,” J. Soc. Inf. Display 2024, 32(5): 309–319.
9M. Kozuma et al., “OLED microdisplay with monolithically integrated CAAC-OS FET and Si CMOS achieved by two-dimensionally arranged silicon display drivers,” IEEE Journal of the Electron Devices Society 2024, 12: 187–194.
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